{"apiVersion":"v1","taxonomyVersion":1,"generatedAt":"2026-10-29T16:39:06.660Z","data":{"recordId":"wsa_qquwqusvx5jh","score":1,"confidence":"high","capped":false,"capReason":null,"sources":[{"n":1,"url":"https://developers.googleblog.com/unifying-edge-ai-how-coral-npus-open-standard-brings-portable-energy-viable-intelligence-from-model-to-silicon/","publisher":"Google","authority":"owner-controlled","verification":"verified","lastRetrievedAt":"2026-10-28T00:15:38.667Z","detectedPublishedAt":"2026-10-20T00:00:00.000Z","rights":"original"}],"claims":[{"id":"16ca2b08-0e4f-446d-a6e8-ecb89fd91cec","kind":"availability","statement":"The complete 32-bit Coral NPU RTL is available today on GitHub.","citations":[{"source":1,"supportProbability":0.98,"supports":true,"quote":{"text":"To help silicon teams bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub.","rights":"original"}}]},{"id":"222a8075-9616-4a98-8ae3-fb7350bbfceb","kind":"capability","statement":"The Matrix Execution Unit is configurable for up to 1 TOPS.","citations":[{"source":1,"supportProbability":0.99,"supports":true,"quote":{"text":"The complete 32-bit Coral NPU architecture (Milestones 1–4): Including our new Matrix Execution Unit , configurable for up to 1 TOPS and targeting 10mW average power for inference.","rights":"original"}}]},{"id":"029d4633-cbca-4b26-9394-e62944a55b19","kind":"capability","statement":"The architecture targets 10mW average power for inference.","citations":[{"source":1,"supportProbability":0.96,"supports":true,"quote":{"text":"The complete 32-bit Coral NPU architecture (Milestones 1–4): Including our new Matrix Execution Unit , configurable for up to 1 TOPS and targeting 10mW average power for inference.","rights":"original"}}]},{"id":"785b672b-fae1-44c2-b6ab-c05d39cbd7ac","kind":"capability","statement":"The Matrix Execution Unit uses a dedicated outer-product multiply-accumulate engine.","citations":[{"source":1,"supportProbability":0.99,"supports":true,"quote":{"text":"Our Matrix Execution Unit leverages the RISC-V VME specification (formally part of the Zvt family) to address this need and uses a dedicated outer-product multiply-accumulate (MAC) engine.","rights":"original"}}]}]},"nextCursor":null,"license":{"catalog":{"name":"CC BY 4.0","spdx":"CC-BY-4.0","url":"https://creativecommons.org/licenses/by/4.0/","attribution":"wowsuchai","attributionUrl":"https://wowsuchai.withglint.app","covers":["catalog metadata","classifications","generated summaries","feed event metadata"]},"excluded":{"covers":["source quotations","linked source content"],"terms":"Not licensed by wowsuchai. Source quotations and linked source content keep their original rights."}}}